Intel 3D-IC STCO Physical Design Engineer in Des Moines, Iowa
The future of Moore's Law: 3D-IC STCO. Link (http://https://www.3dincites.com/2019/08/a-look-inside-the-3d-technology-toolbox-for-stco/)
The Design Technology Pathfinding (DTP) organization in Design Enabling (DE) is chartered to identify and drive key strategic initiatives in pathfinding as a holistic design co-optimization across the product stack from system architecture to silicon as we extend DTCO to STCO. The job requires partnering and leveraging domain experts across Intel and the EDA Eco-System
Run place and route to design convergence to establish STCO 2D-3D Physical design baseline, assess quality, perform design analysis and 3D PPA design co-optimization
3D EDA evaluation and methodology development.
Inter chiplet analysis and validation with Synopsys 3D-IC Compiler and Cadence 3D Integrity
Identify design optimization opportunities: silicon, package, EDA, architecture configuration, methodology, etc.
Analyze architecture critical paths to identify how to best take advantage of this technology
Identify machine learning opportunities for further optimization
Highly independent and self motivated
Creative, Out of the box thinker
This is an internship and compensation will be given accordingly based on candidate education level and internship duration. Responsibilities may be quite diverse of a nonexempt technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually for the summer or for short periods during breaks from school.
You must possess the below requirements to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your schoolwork and/or classes and/or research and/or relevant previous job and/or internship experiences.
- Actively pursuing a MS or PhD degree in Electrical, Computer Engineering or related STEM field.
3+ months of experience with the following:
Physical design, Automated place and route (APR)
Tools, flow and Methodology (TFM) for Design technology co-optimization and PPA
Good understanding of semiconductor physics
Understanding of design methodology and tools features for 2.5D/3D chiplet integration
Experience with high-performance cores
Inside this Business Group
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.
Intel strongly encourages employees to be vaccinated against COVID-19. Intel aligns to federal, state, and local laws and as a contractor to the U.S. Government is subject to government mandates that may be issued. Intel policies for COVID-19 including guidance about testing and vaccination are subject to change over time.
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, and benefit programs. Find more information about our Amazing Benefits here: https://www.intel.com/content/www/us/en/jobs/benefits.html
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.
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