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Facebook Design Implementation Intern (PhD) in Des Moines, Iowa


Facebook's mission is to give people the power to build community and bring the world closer together. Through our family of apps and services, we're building a different kind of company that connects billions of people around the world, gives them ways to share what matters most to them, and helps bring people closer together. Whether we're creating new products or helping a small business expand its reach, people at Facebook are builders at heart. Our global teams are constantly iterating, solving problems, and working together to empower people around the world to build community and connect in meaningful ways. Together, we can help people build stronger communities - we're just getting started.


Facebook Reality Labs (FRL) focuses on delivering Facebook's vision through Augmented Reality (AR) and Virtual Reality (VR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom silicon. Facebook Silicon team is driving the state of the art forward with breakthrough work in computer vision, machine learning, mixed reality, graphics, displays, sensors, and new ways to map the human body. Our chips will enable AR and VR devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistor, through architecture, to firmware and algorithms. This is an opportunity to work with a world-class group of researchers and engineers within the Digital Design Engineering team within AR Silicon. You will use your digital design skills to implement and contribute to development and optimization of state of the art SoCs as well as vision/sensing algorithms.

Required Skills:

  1. End to end performance and power optimization of a custom vector compute unit.

  2. Develop floor plan, power/clock distribution, P&R, timing closure, power and noise analysis.

  3. Explore various microarchitecture and implementation ideas through semi custom design and analyze Power, Performance and Area trade-offs.

  4. Build tools/utility for automated structured datapath design to improve design QoR.

  5. Experiment with various clock tree structures and optimizations.

  6. Through various experiment build simple predictive models to help/assist design implementation.

Minimum Qualifications:

  1. Currently has, or is in the process of obtaining, a PhD degree in Computer Science, Electrical Engineering or related field

  2. Experience with one or more of the following: synthesis, static timing analysis, clock/power distribution and analysis, RC extraction and correlation, place and route, circuit design and analysis

  3. Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment

Preferred Qualifications:

  1. Scripting and programming experience using TCL, Python, Skill and Make

  2. Experience with EDA tools like Design Compiler, ICC2, PrimeTime, Redhawk-SC

  3. Experience with computer arithmetic and analyzing power/performance/area trade-offs for ALU (arithmetic logic unit) components

  4. Intent to return to degree-program after the completion of the internship/co-op

Industry: Internet

Equal Opportunity: Facebook is proud to be an Equal Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Facebook is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at